View MC33879APEK_4464532.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor, inc. reserves t he right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33879 rev. 9.0, 5/2012 freescale semiconductor technical data ? freescale semiconductor, inc. , 2009-2012. all rights reserved. configurable octal serial switch with open load detect current disable the 33879 device is an 8-output hardware configurable, high side / low side switch with 16-bit serial inpu t control using the serial peripheral interface (spi). two of the outputs may be controlled directly via a microcontroller for pulse-width modulation (pwm) applications. the 33879 incorporates smartmos te chnology, with cmos logic, bipolar/mos analog circuitry, and dmos power mosfets. the 33879 controls various inductive, incandescent, or led loads by directly interfacing with a microcontroller. the circuit?s innovative monitoring and protection features include ve ry low standby cu rrents, cascade fault reporting, internal + 45 v clamp voltage for low side configuration, - 20 v high side configuration, output specific diagnostics, and independent over-temperature protection. features ? designed to operate 5.5 v < v pwr < 26.5 v ? 16-bit spi for control and fault reporting, 3.3 v / 5.0 v compatible ? outputs are current limited (0.6 a to 1.2 a) to drive incandescent lamps ? output voltage clamp, + 45 v (low side) and - 20 v (high side) during inductive switching ? on/off control of open load detect current (led application) ? internal reverse batt ery protection on v pwr ? loss of ground or supply will not energize loads or damage ic ? maximum 5.0 a i pwr standby current at 13 v v pwr ?r ds(on) of 0.75 at 25 c typical ? short-circuit detect and current limit with automatic retry ? independent over-temperature protection figure 1. 33879 simplified application diagram high side/ low side switch ek suffix (pb-free) 98arl10543d 32-pin soicw 33879 33879a ordering information device (for tape and reel, add an r2 suffix) temperature range (t a ) package MC33879APEK -40 c to 125 c 32 soicw-ep mc33879tek mcu a0 mosi sclk cs miso pwm1 pwm2 5.0 v v pwr 33879 vdd vpwr en di sclk d0 in5 in6 gnd d1 d2 d3 d4 s1 s2 s3 s4 d5 d6 d7 d8 s5 s6 s7 s8 m cs v bat v bat v bat high side drive low side drive h-bridge configuration
analog integrated circuit device data 2 freescale semiconductor 33879 device variations device variations table 1. device variations characteristic symbol min typ max unit v pwr supply voltage 33879 33879a v pwr -16 -16 ? 40 45 v output fault detection current @ threshold, high side configuration outputs programmed off 33879 33879a i out(flt-th) 35 35 55 55 90 100 a output off open load detection current, high side configuration vdrain = 16 v, vsource = 0 v, outputs programmed off, vpwr = 16 v 33879 33879a i oco 65 60 100 100 160 190 a output off open load detection current, low side configuration vdrain = 16 v, vsource = 0 v, outputs programmed off, vpwr =16 v 333879 338979a i oco 40 40 75 75 135 150 a en pull-down current en = 5.0 v 333879 33879a i en 20 20 45 45 100 110 a
analog integrated circuit device data freescale semiconductor 3 33879 internal block diagram internal block diagram figure 2. 33879 simplifi ed internal block diagram spi bit 4 in5 spi bit 0 ov , por , sleep ~4.0 v open/short threshold ~110 k ~50 a ~50 a vpwr d2 d3 d4 d7 d8 + ? ? + + ? + ? current limit ~80 a ~4.0 v open/short threshold open/short comparator tlim + vdd cs __ sclk di en in5 in6 open load detect current ~80 a gate drive control ? ? internal bias power supply charge pump + do ~50 a over-voltage shutdown/por spi and interface sleep state tlim gate drive control current limit open load detect current enable gnd d1 typical of all 8 output drivers s1 drain outputs s2 s3 s4 s7 s8 source outputs d5 d6 s5 s6 drain outputs source outputs logic open/short comparator ep exposed pad
analog integrated circuit device data 4 freescale semiconductor 33879 pin connections pin connections figure 3. 33879 pin connections table 2. 33879 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition 1 gnd ground ground digital ground. 2 vdd input logic supply voltage logic supply for spi interface. with v dd low the device will be in sleep mode. 3 s8 output source output 8 output 8 mosfet source pin. 4, 8, 9, 24, 25, 30 nc no connection not connected no internal connection to this pin. 5 d8 output drain output 8 output 8 mosfet drain pin. 6 s2 output source output 2 output 2 mosfet source pin. 7 d2 output drain output 2 output 2 mosfet drain pin. 10 s1 output source output 1 output 1 mosfet source pin. 11 d1 output drain output 1 output 1 mosfet drain pin. 12 d6 output drain output 6 output 6 mosfet drain pin. 13 s6 output source output 6 output 6 mosfet source pin. 14 in6 input command input 6 pwm direct control input pin for out put 6. in6 is ?or? with spi bit. 15 en input enable input ic enable. active high. with en low, the device is in sleep mode. 16 sclk clock spi clock spi control clock input pin. 17 di input serial data input spi control data input pin from mcu to the 33879. logic [1] activates output. 18 cs input spi chip select spi control chip select input pin from mcu to the 33879. logic [0] allows data to be transferred in. 19 in5 input command input 5 pwm direct control input pin for out put 5. in5 is ?or? with spi bit. 20 s5 output source output 5 output 5 mosfet source pin. do 1 d7 s4 d4 nc nc s3 d3 d5 s5 cs di in5 s7 vpwr nc gnd d8 s2 d2 nc nc s1 d1 d6 s6 en sclk in6 nc vdd s8 8 9 10 11 12 13 14 15 16 3 4 5 6 7 2 32 25 24 23 22 21 20 19 18 17 30 29 28 27 26 31 gnd
analog integrated circuit device data freescale semiconductor 5 33879 pin connections 21 d5 output drain output 5 output 5 mosfet drain pin. 22 d3 output drain output 3 output 3 mosfet drain pin. 23 s3 output source output 3 output 3 mosfet source pin. 26 d4 output drain output 4 output 4 mosfet drain pin. 27 s4 output source output 4 output 4 mosfet source pin. 28 d7 output drain output 7 output 7 mosfet drain pin. 29 s7 output source output 7 output 7 mosfet source pin. 31 vpwr input battery input power supply pin to the 33879. v pwr has internal reverse battery protection. 32 do output serial data output spi control data output pin from the 33879 to the mcu. do = 0 no fault, do = 1 specific output has fault. 33 ep ground exposed pad device will perform as specifi ed with the exposed pad un-terminated (floating) however, it is recommended that the exposed pad be terminated to pin 1 (gnd) and system ground. table 2. 33879 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33879 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. 33879 maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings v dd supply voltage (1) v dd - 0.3 to 7.0 v dc cs , di, do, sclk, in5, in6, and en (1) ? - 0.3 to 7.0 v dc v pwr supply voltage (1) 33879 33879a v pwr -16 to 40 -16 to 45 v dc output clamp energy (2) e clamp 50 mj esd voltage (3) human body model 33879 machine model 33879 human body model 33879a machine model 33879a v esd1 v esd2 v esd1 v esd2 450 100 2000 200 v thermal ratings operating temperature ambient junction case t a t j t c - 40 to 125 - 40 to 150 - 40 to 125 c storage temperature t stg - 55 to 150 c power dissipation (4) p d 1.7 w thermal resistance junction to ambient between the die and the exposed die pad r ja r jc 71 1.2 c/w peak package reflow temperature during reflow (5) , (6) t pprt note 6 c notes 1. exceeding these limits may cause malf unction or permanent damage to the device. 2. maximum output clamp energy capability at 150 c junction temperature using single non- repetitive pulse method with i = 350 ma. 3. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ). 4. maximum power dissipation at t a = 25 c with no heatsink used. 5. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 6. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data freescale semiconductor 7 33879 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 3.1 v v dd 5.5 v, 5.5 v v pwr 18 v, - 40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit power input supply voltage range fully operational 33879 33879a v pwr (fo) 5.5 5.5 ? ? 26.5 27.5 v supply current i pwr (on) ? 14 24 ma sleep state supply current v dd or en 0.8 v, v pwr = 13 v i pwr (ss) ? 2.0 5.0 a sleep state supply current en 0.8 v, v dd = 5.5 v i vdd (ss) ? 2.0 5.0 a v pwr over-voltage shutdown threshold voltage 33879 33879a v pwr( ov) 27 28 28.5 30 32 33 v v pwr over-voltage shutdown hysteresis voltage v pwr(ov-hys) 0.2 1.5 2.5 v v pwr under-voltage shutdown threshold voltage v pwr( uv) 3.0 4.0 5.0 v v pwr under-voltage shutdown hysteresis voltage v pwr( uv-hys) 300 500 700 mv logic supply voltage v dd 3.1 ? 5.5 v logic supply current i dd 250 400 700 a logic supply sleep state threshold voltage v dd(ss) 0.8 2.5 3.0 v
analog integrated circuit device data 8 freescale semiconductor 33879 electrical characteristics static electrical characteristics power output drain-to-source on resistance (i out = 0.350 a, v pwr = 13 v) t j = 125 c t j = 25 c t j = -40 c r ds (on) ? ? ? ? 0.75 ? 1.4 ? ? output self limiting current high side and low side configurations i out (lim) 0.6 ? 1.2 a output fault detection voltage threshold (7) outputs programmed off v out(flt-th) 2.5 4.0 4.5 v output fault detection current @ threshold, high side configuration outputs programmed off 33879 33879a i out(flt-th) 35 35 55 55 90 100 a output fault detection current @ threshold, low side configuration outputs programmed off i out(flt-th) 20 30 60 a output off open load detection current, high side configuration v drain = 16 v, v source = 0 v, outputs programmed off, v pwr = 16 v 33879 33879a i oco 65 60 100 100 160 190 a output off open load detection current, low side configuration v drain = 16 v, v source = 0 v, outputs programmed off, v pwr =16 v 33879 33879a i oco 40 40 75 75 135 150 a output clamp voltage low side drive i d = 10 ma v oc (lsd) 40 45 55 v output clamp voltage high side drive i s = -10 ma v oc (hsd) -15 - 20 - 25 v output leakage current high side and low side configurations v dd = 0 v, v drain = 16 v, v source = 0 v i out (lkg) ? ? 5.0 a output leakage current low side configuration v dd = 5.0 v, v drain = 16 v, v source = 0 v, open load detection current disabled i out (lkg) ? ? 5.0 a output leakage current high side configuration v dd = 5.0 v, v drain = 16 v, v source = 0 v, open load detection current disabled i out (lkg) ? ? 20 a over-temperature shutdown (8) t lim 155 ? 185 c over-temperature shutdown hysteresis (8) t lim (hys) 5.0 10 15 c notes 7. output fault detection thresholds with outputs programmed off. output fault detect thresholds are the same for output open an d shorts. 8. this parameter is guaranteed by desi gn; however, it is not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 3.1 v v dd 5.5 v, 5.5 v v pwr 18 v, - 40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33879 electrical characteristics static electrical characteristics digital interface input logic high-voltage thresholds (9) v ih 0.7 v dd ? v dd + 0.3 v input logic low-voltage thresholds (9) v il gnd - 0.3 ? 0.2 v dd v in5, in6, en input logic current in5, in6, en = 0 v i in5, i in6, i en -10 ? 10 a in5, in6 pull-down current 0.8 to 5.0 v i in5, i in6, 30 45 100 a en pull-down current en = 5.0 v 33879 33879a i en 20 20 45 45 100 110 a sclk, di input, tri-state do output 0 to 5.0 v i sck, i di, i tri- do -10 ? 10 a cs input current cs = v dd i cs -10 ? 10 a cs pull-up current cs = 0 v i cs -30 ? -100 a cs leakage current to v dd cs = 5.0 v, v dd = 0 v i cs(lkg) ? ? 10 a do high state output voltage i do-high = -1.6 ma v dohigh v dd - 0.4 ? v dd v do low state output voltage i do-low = 1.6 ma v dolow ? ? 0.4 v input capacitance on sclk, di, tri-state do, in5, in6, en (10) c in ? ? 20 pf notes 9. upper and lower logic threshold voltage levels apply to di, cs , sclk, in5, in6, and en. 10. this parameter is guaranteed by desi gn; however, it is not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 3.1 v v dd 5.5 v, 5.5 v v pwr 18 v, - 40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33879 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 3.1 v v dd 5.5 v, 5.5 v v pwr 18 v, - 40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit power output timing output slew rate low side configuration (11) r load = 620 , c l = 200pf t sr(rise) 0.1 0.5 1.0 v/ s output slew rate low side configuration (11) r load = 620 , c l = 200 pf t sr(fall) 0.1 0.5 1.0 v/ s output rise time high side configuration (11) r load = 620 , c l = 200 pf t sr(rise) 0.1 0.3 1.0 v/ s output fall time high side configuration (11) r load = 620 , c l = 200 pf t sr(fall) 0.1 0.3 1.0 v/ s output turn on delay time, high side and low side configuration (12) t dly(on) 1.0 15 50 s output turn off delay time, high side and low side configuration (12) t dly(off) 1.0 30 100 s output fault delay time (13) t fault 100 ? 300 s power-on reset delay delay time required from rising edge of en and v dd to spi active t por 100 ? ? s low-state duration on v dd or en for reset v dd or en 0.2 v t reset 100 ? ? s notes 11. output slew rate respec tively measured across a 620 resistive load at 10 to 90 percent and 90 to 10 percent voltage points. c l capacitor is connected from drain or source output to ground. 12. output turn on and off delay time measured from 50 percent rising edge of cs to the beginning of the 10 and 90 percent transition points. 13. duration of fault before fault bit is set. duration between access times must be greater than 300 s to read faults.
analog integrated circuit device data freescale semiconductor 11 33879 electrical characteristics timing diagrams timing diagrams figure 4. spi timing diagram digital interface timing (14) recommended frequency of spi operation (14) f spi ? 4.0 ? mhz falling edge of cs to rising edge of sclk (required setup time) t lead 100 ? ? ns falling edge of sclk to rising edge of cs (required setup time) t lag 50 ? ? ns di to falling edge of sclk (required setup time) t di (su) 16 ? ? ns falling edge of sclk to di (required hold time) t di (hold) 20 ? ? ns di, cs , sclk signal rise time (15) t r (di) ? 5.0 ? ns di, cs , sclk signal fall time (15) t f (di) ? 5.0 ? ns time from falling edge of cs to do low-impedance (16) t do (en) ? ? 55 ns time from rising edge of cs to do high-impedance (17) t do (dis) ? ? 55 ns time from rising edge of sclk to do data valid (18) t valid ? 25 55 ns notes 14. this parameter is guaranteed by desi gn. production test equipment uses 4.16 mhz, 5.5 v/3.1 v spi interface. 15. rise and fall time of incoming di, cs , and sclk signals suggested for design consideration to prevent the occurrence of double pulsing. 16. time required for output status data to be available for use at do pin. 17. time required for output status data to be terminated at do pin. 18. time required to obtain valid data out from do following the rise of sclk. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 3.1 v v dd 5.5 v, 5.5 v v pwr 18 v, - 40 c t c 125 c, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit t do(dis) 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t do(en) t di(su) t di(hold) t valid t lag cs sclk di do msb in msb out lsb out 0.7 v dd 0.2 v dd
analog integrated circuit device data 12 freescale semiconductor 33879 electrical characteristics typical electrical characteristics figure 5. valid data delay time and valid time test circuit figure 6. valid data delay time and valid time waveforms figure 7. enable and disable time waveforms typical electrical characteristics figure 8. i pwr vs. temperature figure 9. sleep state i pwr vs. temperature do c l = 200 pf v dd = 5.0 v sclk 33879 under te s t note: c l represents the total capacitance of the test fixture and probe. (low-to-high) t f(di t r(di) 0.2 v dd 0.7 v dd 0.2 0.7 v dd t valid t r(do v ol v oh v ol v oh 0.2 v dd 0.7 v dd 0 v 3.3/5.0 v < 50 ns 50% < 50 ns do sclk (high-to-low) do 90% t f(cs) t r(cs) v oh v ol 0 v 3.3/5.0 v do t do(dis) t do(en) t do(dis) t do(en) (tri-state to low) 0.7 v dd 0.2 v dd < 50 ns < 50 ns cs 90% do (tri-state to high) 10% 10% 90% 10% v tri-state v tri-state 02550 100125 -40 75 -25 i pwr current into v pwr pin (ma) 14 15 16 17 18 19 20 t a, ambient temperature ( ? c v pwr @ 18 v 33879 33879a 0 25 50 100 125 -40 75 -25 i pwr current into v pwr pin (?a 1 2 3 4 5 6 7 t a, ambient temperature ( ? c v pwr @ 13 v
analog integrated circuit device data freescale semiconductor 13 33879 electrical characteristics typical electrical characteristics figure 10. sleep state i pwr vs. v pwr figure 11. r ds(on) vs. temperature at 350 ma figure 12. r ds(on) vs. v pwr at 350 ma figure 13. open load detection current at threshold figure 14. open load detection threshold vs. temperature 510152025 0 i pwr current into v pwr pin (?a 20 40 60 80 100 120 140 v pwr t a = 25 ? 33879 33879a 02550 100125 -40 75 -25 0.4 0.6 0.8 1.0 1.2 1.4 t a, ambient temperature ( ? c v pwr @ 13 v r ds(on) ( ) high side drive 0.2 0.4 0.6 1.0 1.2 v pwr (v) 5 10152025 0 r ds(on) ( ) 0.8 1.4 t a = 25 ? high side drive 0 25 50 100 125 -40 75 -25 i oco, open load (?a 20 40 60 80 100 120 140 t a, ambient temperature ( ? c v pwr @ 13 v high side low side 02550 100125 -40 75 -25 v out(flt-th), open load threshold (v) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t a, ambient temperature ( ? c v pwr @ 13 v high side and low side
analog integrated circuit device data 14 freescale semiconductor 33879 functional description functional pin description functional description functional pin description cs pin the system mcu selects the 33879 with which to communicate through the use of the chip select cs pin. logic low on cs enables the data output (do) driver and allows data to be transferred from t he mcu to the 33879 and vice versa. data clocked into the 33879 is acted upon on the rising edge of cs . to avoid any spurious data, it is essential the high-to-low transition of the cs signal occur only wh en spi clock (sclk) is in a logic low state. sclk pin the sclk pin clocks the inter nal shift registers of the 33879. the serial data input (di) pin is latched into the input shift register on the falling edge of the sclk. the serial data output (do) pin shifts data out of the shift register on the rising edge of the sclk signal. false clocking of the shift register must be avoided to ensure validity of data. it is essential that the sclk pin be in a logic low state when the cs pin makes any transition. for this reason, it is recommended the sclk pin is commanded to a logic low state when the device is not accessed ( cs in logic high state). with cs in a logic high state, si gnals present on sclk and di are ignored and the do output is tri-state. di pin the di pin is used for serial instruction data input. di information is latched into the input register on the falling edge of sclk. a logic high state present on di will program a specific output on . the specific output will turn on with the rising edge of the cs signal. conversely, a logic low state present on the di pin will program the output off . the specific output will turn off with the rising edge of the cs signal. to program the eight outputs and open load detection current on or off , send the di data beginning with the open load detection current bits, follo wed by output eight, output seven, and so on to output o ne. for each falling edge of the sclk while cs is logic low, a data bit instruction ( on or off) is loaded into the shift register per the data bit di state. sixteen bits of entered information is required to fill the input shift register. do pin the do pin is the output from the shift register. the do pin remains tri-state until the cs pin is in a logic low state. all faults on the 33879 device are reported as logic [1] through the do data pin. regardless of the configuration of the driver, open loads and shorted loads are reported as logic [1]. conversely, normal operating outputs with non-faulted loads are reported as logic [0]. outputs programmed with open load detection current disabled will report logic [0] in the off state. the first eight positive transitions of sclk will report logic [0] followed by the status of the eight output drivers. the di / do shifting of data follows a first-in, first-out protocol with both input and output words tr ansferring the most significant bit (msb) first. en pin the en pin on the 33879 enables the device. with the en pin high, output drivers may be activated and open / short fault detection performed and reported. with the en pin low, all outputs become inactive, open load detection current is disabled, and the device enters sleep mode. the 33879 will perform power-on reset on rising edge of the enable signal. in5 and in6 pins the in5 and in6 command inputs allow outputs five and six to be used in pwm applications. the in5 and in6 pins are or-ed with the serial peripheral interface (spi) command input bits. for spi control of outputs five and six, the in5 and in6 pins should be grounded or held low by the microprocessor. when using in5 or in6 to pwm the output, the control spi bit must be logic [0]. maximum pwm frequency for each output is 2.0 khz. vdd pin the vdd input pin is used to determine logic levels on the microprocessor interface (spi) pins. current from vdd is used to drive do output and the pullup current for cs . v dd must be applied for normal mode operation. the 33879 device will perform power-on reset with the application of v dd. vpwr pin the v pwr pin is battery input and power-on reset to the 33879 ic. the vpwr pin has internal reverse battery protection. all internal logic current is provided from the vpwr pin. the 33879 will perform power-on reset with the application of v pwr. d1? d8 pins the d1 to d8 pins are the ope n-drain outputs of the 33879. for high side drive configurations, the drain pins are connected to battery supply. in low side drive configurations, the drain pins are connected to the low side of the load. all outputs may be configured individually as desired. when configured as low side drive, the 33879 limits the positive inductive transient to 45 v. s1? s8 pins the s1 to s8 pins are the source outputs of the 33879. for high side drive configurations, the source pins are connected directly to the load. in low side drive configurations, the
analog integrated circuit device data freescale semiconductor 15 33879 functional description mcu interface description source is connected to ground. all outputs may be configured individually as desired. when high side drive is used, the 33879 will limit the negative inductive transient to negative 20 v. exposed pad pin device will perform as specified with the exposed pad un- terminated (floating) however, it is recommended that the exposed pad be terminated to pin 1 (gnd) and system ground. mcu interface description introduction the 33879 is an 8-output hardware-configurable power switch with 16-bit serial contro l. a simplified internal block diagram of the 33879 is shown in figure 2 on page 3 . the 33879 device uses high-efficiency up-drain power dmos output transistors exhibiting low drain-to-source on resistance (r ds(on) = 0.75 at 25 c typical) and dense cmos control logic. all out puts have independent voltage clamps to provide fast inductive turn-off and transient protection. in operation, the 33879 functi ons as an 8-output serial switch serving as a mcu bus expander and buffer with fault management and fault reportin g features. in doing so, the device directly relieves the mcu of the f ault management functions. this device directly interfaces to an mcu using a spi for control and diagnostic readout. figure 15 illustrates the basic spi configuration between an mcu and one 33879. figure 15. spi interface with microcontroller all inputs are compatible with 5.0 v and 3.3 v cmos logic levels and incorporate positiv e logic. when a spi bit is programmed to a logic [0], the corresponding output will be off. conversely, when a spi bit is programmed to logic [1] the output being controlled will be on. diagnostics are treated in a similar manner. ou tputs with a fault will feed back (via do) a logic [1] to the microcontroller, while normal operating outputs will provide a logic [0]. figure 16 illustrates the daisy chain configuration using the 33879. data from the mcu is clocked daisy chain through each device while the cs bit is commanded low by the mcu. during each clock cycle, output st atus from the daisy chain is transferred to the mcu via t he master in slave out (miso) line. on rising edge of cs, command data stored in the input register is then transferred to the output driver. figure 16. 33879 spi system daisy chain multiple 33879 devices can be controlled in a parallel input fashion using the spi. figure 17 illustrates th e control of 24 loads using three dedicated parallel mcu ports for chip select. figure 17. parallel input spi control receive buffer parallel ports to logic 33879 mc68hcxx microcontroller do di cs sclk miso mosi shift register shift register 16 bits 16 bits mc68hcxx microcontroller with spi interface 8 outputs 8 outputs 8 outputs cs miso mosi parallel port sclk do di do di do di cs cs sclk sclk 33879 33879 33879 di di di sclk sclk sclk do do do cs cs cs parallel ports mosi miso sclk 8 outputs 8 outputs 8 outputs mc68hcxx microcontroller with spi interface a b c 33879 33879 33879
analog integrated circuit device data 16 freescale semiconductor 33879 functional description spi definition spi definition on each spi communication, a 16-bit command word is sent to the 33879 and a 16-bit status word is received from the 33879. the msb is sent and received first. as table shows, the command register defines the position and operation the 33879 will perform on rising edge of cs . the fault register, shown in table 6 , defines the previous state status of the output driver. table identifies the type of fault and the method by which the fault is communicated to the microprocessor 0 = bits 0 to 7, output commanded off. 0 = bits 8 to 15, open load detection current off. 1 = bits 0 to 7, output commanded on. 1 = bits 8 to 15 open load detection current on. 0 = bits 0 to 7, no fault at output. 1 = bits 0 to 7, output short-to-battery, short-to-gnd, open load, or t lim . bits 8 to 15 will always return ?0?. table 6. command register definition msb lsb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 on / off open load detect 8 on / off open load detect 7 on / off open load detect 6 on / off open load detect 5 on / off open load detect 4 on / off open load detect 3 on / off open load detect 2 on / off open load detect 1 on / off out 8 on / off out 7 on / off out 6 on / off out 5 on / off out 4 on / off out 3 on / off out 2 on / off out 1 table 7. fault register definition msb lsb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 0 0 out 8 status out 7 status out 6 status out 5 status out 4 status out 3 status out 2 status out 1 status table 8. fault operation serial output (do) pin reports over-temperature fault reported by serial output (do) pin. over-current do pin reports short to battery/s upply or over-current condition. output on open load fault not reported. output off open load fault do pin reports output off open load condition only with open load detection current enabled. do pin will report ?0? for output off open load f ault with open load detection current disabled. device shutdowns over-voltage total device shutdown at v pwr = v pwr(ov) v. resumes normal operation with proper voltage. all outputs assuming the previous state upon recovery from over-voltage. over-temperature only the output experiencing an over-temperature shuts down. output assumes previous state upon recovery from over-temperature.
analog integrated circuit device data freescale semiconductor 17 33879 functional description device operation device operation power supply the 33879 device has been designed with ultra-low sleep mode currents. the device may enter sleep mode via the en pin or the v dd pin. in the sleep mode (en or v dd 0.8 v), the current consumed by the v pwr pin is less than 5.0 a. placing the 33879 in sleep mode resets the internal registers to the power-on rese t state. the reset state is defined as all outputs off and open load detection current disabled. to place the 33879 in the sleep mode, either command all outputs off and apply logic low to the en input pin or remove power from the vdd supply pin. prior to removing v dd from the device, it is recommended that all control inputs from the mcu be low. paralleling of outputs using mosfets as an output switch conveniently allows the paralleling of outputs for increased current capability. r ds(on) of mosfets have an inher ent positive temperature coefficient that provides balanced current sharing between outputs without destructive oper ation. this mode of operation may be desirable in the event the application requires lower power dissipation or the added c apability of switching higher currents. performance of para llel operation results in a corresponding decrease in r ds(on) while the output off open load detection currents and the output current limits increase correspondingly. paralleling outputs from two or more different ic devices is possible but not recommended. fault logic operation fault logic of the 33879 devic e has been greatly simplified over other devices using spi communications. as command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the mcu. regardless of the conf iguration, with no outputs faulted and open load detection current enabled, all status bits being received by the mcu will be zero. when outputs are faulted (off state open circui t or on state short-circuit / over-temperature), the status bi ts being received by the mcu will be one. the distinction between open circuit fault and short / over-temperature is comple ted via the command word. for example, when a zero command bit is sent and a one fault is received in the following word, the fault is open / short- to-battery for high side drive or open / short-to-ground for low side drive. in the same manner, when a one command bit is sent and a one fault is received in the following word, the fault is a short-to-ground / over-temperature for high side drive or short-to-battery/over-temperature for low side drive. the timing between two write words must be greater than 300 s to allow adequate time to sense and report the proper fault status. spi integrity check checking the integrity of the spi communication with the initial power-up of the v dd and en pins is recommended. after initial system start-up or reset, the m cu will write one 32-bit pattern to the 33879. the first 16 bits read by the mcu will be 8 logic [0]s followed by the fault status of the outputs. the second 16 bits will be the same bit pattern sent by the mcu. by the mcu receiving the same bit pattern it sent, bus integrity is confirmed. please note the second 16-bit pattern the mcu sends to the device is the command word and will be transferred to the outputs with rising edge of cs . important a sclk pulse count strategy has been implemented to ensure integrit y of spi communications. spi messages consisting of 16 sclk pulses and multiples of 8 clock pulses thereafter will be acknowledged. spi messages consisting of other than 16 + multiples of 8 sclk pulses will be ignored by the device. over-temperature fault over-temperature detection and shutdown circuits are specifically incorporated for each individual output. the shutdown following an over-temperature condition is independent of the system clock or any other logic signal. each independent output shuts down at 155 c to 185 c. when an output shuts down owing to an over-temperature fault, no other outputs are affe cted. the mcu recognizes the fault by a one in the fault status register. after the 33879 device has cooled below the switch point temperature and 15 c hysteresis, the output will ac tivate unless told otherwise by the mcu via spi to shut down. over-voltage fault an over-voltage condition on the vpwr pin will cause the device to shut down all outputs until the over-voltage condition is removed. when the over-voltage condition is removed, the outputs will resume their previous state. this device does not detect an over-voltage on the v dd pin. the over-voltage threshold on the v pwr pin is specified as v pwr(ov) v, with 1.0 v typical hysteresis. a v pwr over- voltage detection is global , causing all outputs to be turned off. output off open load fault an output off open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). the output off open load fault is detected by comparing the drain-to-source voltage of the specific mosfet output to an internally generated reference. each output has one dedicated comparator for this purpose. an output off open load fault is indicated when the drain- to-source voltage is less than the output threshold voltage (v out(flt-th) ) of 2.5 v to 4.0 v. hence, the 33879 will
analog integrated circuit device data 18 freescale semiconductor 33879 functional description device operation declare the load open in the off state when the output drain- to-source voltage is less than v out(flt-th) . this device has an internal 80 a current source connected from drain to source of the output mosfet. the current source may be programmed on or off via spi. the power-on reset state for the curr ent source is ?off? and must be enabled via spi. to achieve low sleep mode quiescent currents, the open load detection current source of each driver is switched off when v dd or en is removed. during output switching, especi ally with capacitive loads, a false output off open load fault may be triggered. to prevent this false fault from being reported, an internal fault filter of 100 s to 300 s is incorporated. a false fault reporting is a function of the load impedance, r ds(on) , c out of the mosfet, as well as the supply voltage, v pwr . the rising edge of cs triggers the built-in fault delay timer. the timer will time out before the fault comparator is enabled and the fault is detected. once the condition causing the open load fault is removed, the device will resume normal operation. the open load fault, however, will be latched in the output do register for the mcu to read. shorted load fault a shorted load (over-current) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. there are two safety circuits progressively in operation during load short conditions t hat provide system protection: 1. the device?s output current is monitored in an analog fashion using sensefet approach and current limited. 2. the device?s output therma l limit is sensed and when attained causes only the spec ific faulted output to shut down. the output will remain off until cooled. the device will then reassert th e output automat ically. the cycle will continue until fault is removed or the command bit instructs the output off. shorted load faults will be reported properly through the spi regardless of open load detection current enable bits. under-voltage shutdown an under-voltage condition on v dd or v pwr will result in the shutdown of all outputs. the v dd under-voltage threshold is between 0.8 and 3.0 v. v pwr under-voltage threshold is between 3.0 and 5.0 v. when the supplies fall below their respective thresholds, all outputs are turned off. as both supplies returns to normal levels , internal logi c is reset and the device resumes normal operation. output voltage clamp each output of the 33879 inco rporates an internal voltage clamp to provide fast turn-off and transient protection of each output. each clamp independently limits the drain-to-source voltage to 45 v for low side drive configurations and -20 v for high side drive configurations. the total energy clamped (e j ) can be calculated by multiplying the current area under the current curve (i a ) times the clamp voltage (v cl ) (see figure 18 ). characterization of the output clamps, using a single pulse non-repetitive method at 0.35 a, indicates the maximum energy per output to be 50 mj at 150 c junction temperature. figure 18. output voltage clamping spi configurations the spi configuration on the 33879 device is consistent with other devices in the octal serial switch (oss) family. this device may be used in serial spi or parallel spi with the 33298 and 33291. different spi configurations may be provided. for more information, contact freescale analog products division or the local freescale representative. reverse battery the 33879 has been designed with reverse battery protection on the v pwr pin. all outputs consist of a power mosfet with an integral substrate diode. during the reve rse battery condition, current will flow through the load via the substrate diode. under this circumstance, relays may energize and lamps will turn on. where load reverse battery protection is desired, a reverse battery blocking diode must be placed in series with the load. current area (i a ) clamp energy (e j = i a x v cl ) clamp energy (e j = i a x v cl ) drain voltage source voltage time time bat drain-to-source clamp voltage (v cl = 45 v) drain current (id = 0.3 a) gnd gnd vs drain-to-source on voltage (v ds(on) ) drain-to-source on voltage (v ds(on) ) current area (i a ) source current (i s = 0.3 a) source clamp voltage (v cl = -15 v)
analog integrated circuit device data freescale semiconductor 19 33879 packaging package dimensions packaging package dimensions important: for the most current revision of the package, visit www.freescale.com and perform a keyword search using the ?98arl10543d? drawing number listed below. dimensions shown are provided for reference only. ek (pb-free) suffix 32-lead soicw exposed pad 98arl10543d issue c
analog integrated circuit device data 20 freescale semiconductor 33879 packaging package dimensions package dimensions (continued) ek (pb-free) suffix 32-lead soicw exposed pad 98arl10543d issue c
analog integrated circuit device data freescale semiconductor 21 33879 packaging package dimensions ek (pb-free) suffix 32-lead soicw exposed pad 98arl10543d issue c
analog integrated circuit device data 22 freescale semiconductor 33879 revision history revision history revision date description of changes 5.0 2/2006 ? page 2, figure 1; an exposed pad internal block and ep pin have been added to the internal block diagram. ? page 4, table 1; table 1 has been updated to reflect the exposed pad pin and pin definition. ? page 6, table 3; logic supply sleep state hysteresis and note 7 have been removed. the vdd supply contains no hysteresis. ? page 7, table 3; output fault detection cu rrent @ threshold, high-side configuration max parameter has been increased from 70ua to 90ua. ? page 7, table 3; output off open load detection current, high-side configuration has been updated to reflect the voltage of the vpwr pin during the parameter test. ? page 7, table 3; output off open load de tection current, low-side configuration has been updated to reflect the voltage of the vpwr pin during the parameter test. ? page 7, table 3; output leakage current high-side and low-side configuration max parameter has been decreased from 7ua to 5ua. ? page 15, functional pin description; a description has been added for the exposed pad pin. ? page 1, device isometric; corrected orientatio n of ic pin 1 from top left to bottom right. ? all pages; updated data sheet to reflect freescale formatting. 6.0 6/2007 ? added 33879a version ? added mcz33879ek/r2 and mcz33879aek/r2 to the ordering information ? added device variations on page 2 ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum rations on page 6 . added note with instructions from www.freescale.com. ? changed output fault detection voltage threshold (7) on page 8 ? renumbered x axis on figure 14 - open load detection threshold vs. temperature on page 13 ? changed over-voltage on page 16 and over-voltage fault on page 17 7.0 8/2008 ? updated package drawing. 8.0 10/2009 ? updated data sheet status from advance information to technical data ? updated to the current freescale form and style 9.0 5/2012 ? removed mc33879ek from the ordering information ? removed mcz33879aek and added MC33879APEK to the ordering information ? removed mcz33879ek and added mc33879tek to the ordering information ? updated output fault detection current @ threshold, high side configuration on page 8 ? updated output off open load detection current, high side configuration on page 8 ? updated output off open load detection current, low side configuration on page 8 ? updated en pull-down current on page 9 ? updated the freescale form and style
document number: mc33879 rev. 9.0 5/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

▲Up To Search▲

Price & Availability of MC33879APEK

	To Download MC33879APEK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .